1. Field of the Invention
The present invention relates to a nonvolatile memory device driving method, a semiconductor storage device, and a liquid crystal display device including the semiconductor storage device.
2. Description of the Related Art
There is known a flash memory whose memory cells each include a control gate and a charge storage layer and have a MOS transistor structure in which electric charges are injected into and released from the charge storage layer by utilizing an FN tunnel current. Data “0” and “1” are stored according to a difference in threshold voltage attributable to a difference in the charge storage state of the charge storage layer. In the case of an N-channel memory cell having a floating gate as the charge storage layer, for example, a high voltage is applied to the control gate, and a drain diffusion layer, a source diffusion layer and a semiconductor substrate are grounded for the injection of electric charges into the floating gate. At this time, the electric charges are injected into the floating gate from the substrate by the FN tunnel current.
Thus, the threshold voltage of the memory cell is positively shifted by the injection of the electric charges. For the release of the electric charges from the floating gate, on the other hand, a negative voltage is applied to the control gate, and the drain diffusion layer, the source diffusion layer and the substrate are grounded. At this time, the electric charges are released from the floating gate to the substrate by the FN tunnel current. Thus, the threshold voltage of the memory cell is negatively shifted by the release of the electric charges.
In the aforesaid operation, the ratio (coupling ratio) between a floating gate/control gate coupling capacitance and a floating gate/substrate coupling capacitance is important for efficiently achieving the charge injection and the charge release, i.e., for the writing and the erasing. As the capacitance between the floating gate and the control gate is increased, the potential of the control gate can more effectively be transferred to the floating gate, thereby facilitating the writing and the erasing.
With the recent progress of the semiconductor technology, particularly the micro-processing technology, the size reduction and capacity increase of memory cells of nonvolatile memory devices are rapidly promoted. Therefore, how to reduce the area of the memory cells and how to increase the capacitance between the floating gate and the control gate are critical issues. In order to increase the capacitance between the floating gate and the control gate, it is necessary to reduce the thickness of a gate insulation film provided between the floating gate and the control gate, to increase the dielectric constant of the gate insulation film, or to increase the area of opposed surfaces of the floating gate and the control gate. However, the thickness reduction of the gate insulation film has limitation in consideration of the reliability. A conceivable approach to the increase of the dielectric constant of the gate insulation film is to employ a silicon nitride film or the like instead of a silicon oxide film. However, this approach poses a problem associated with the reliability and, hence, is not practical. Therefore, it is necessary to increase an overlap between the floating gate and the control gate to not smaller than a predetermined area in order to provide a sufficient capacitance. However, this is contradictory to the reduction of the area of the memory cells for the increase of the storage capacity of the nonvolatile memory device.
On the other hand, a nonvolatile memory device as shown in FIG. 7 is known (see, for example, Japanese Unexamined Patent Publication No. Hei 4-79369 (1992)). In the nonvolatile memory device shown in FIG. 7, memory cells are constructed by utilizing peripheral walls of a plurality of island semiconductor layers 12 arranged in a sea-island configuration or a plurality of island semiconductor layers 12 arranged in a matrix configuration and isolated from each other by a lattice trench formed in a semiconductor substrate 13. The island semiconductor layers 12 are each formed with two memory cells, and selection transistors are provided above and below the memory cells. The memory cells are constituted by a drain diffusion layer 7 provided as a drain in an upper surface of the island semiconductor layer, a common source diffusion layer 11 provided as a source in a bottom of the trench, and charge storage layers 1, 3 and control gates 2, 4 entirely surrounding the peripheral surface of the island semiconductor layer 12. A control gate line is provided along each row of island semiconductor layers 12 serially arranged and connected to the control gates 2, 4. A bit line is provided as intersecting the control gate line and connected to the drain diffusion layers 7 of a plurality of such nonvolatile memory devices.
In the memory cell structure shown in FIG. 7, the selection transistors each include a selection gate electrode 5, 6 which at least partly surrounds the peripheral surface of the island semiconductor layer 12 and is connected in series to the memory cells so as to prevent an electric current from flowing into unselected cells even if the memory cells are over-erased (with a read voltage of 0V and a negative threshold). Thus, the aforesaid problem can assuredly be eliminated.
It is herein assumed that memory cells connected in series on each of the island semiconductor layers as shown in FIG. 7 have the same threshold voltage in the non-volatile memory device. Here, a reading operation is performed by applying a read potential sequentially to control gate lines (CG) of the memory cells for determination of “0” or “1” depending on the presence or absence of the electric current. If the electric current flowing through the semiconductor layer causes a potential difference between the memory cells connected in series on the single island semiconductor layer due to a resistant component of the semiconductor layer at this time, the potential difference makes the threshold voltages of the respective memory cells non-uniform (back bias effect). The back bias effect limits the number of memory cells to be connected in series, thereby hampering the attempt at the increase of the capacitance. Further, the back bias effect may occur not only where a plurality of devices are connected in series on the single island semiconductor layer, but also where a single memory cell is provided in the single island semiconductor layer. That is, where the back bias effect varies depending on the position on the semiconductor substrate, the threshold voltages of the respective memory cells are liable to be non-uniform. If the threshold voltages are non-uniform depending on the positions of the memory cells, the write/erase/read voltages for the writing, erasing and reading operations with respect to the memory cells are liable to be non-uniform, resulting in adverse effects such as variations in the characteristics of the memory devices.
To solve the problem associated with the back bias effect of the substrate, an improved arrangement is proposed in which island semiconductor layers are electrically isolated from a semiconductor substrate (see, for example, Japanese Unexamined Patent Publication No. 2002-57231). By thus electrically isolating the island semiconductor layers from the semiconductor substrate, the back bias effect can be suppressed. Thus, a nonvolatile memory device having an improved integration density is provided, in which the coupling ratio of the floating gate/control gate coupling capacitance is further increased without increasing the area of the memory cells, and the variations in cell characteristics attributable to the production process are suppressed.
From another viewpoint, it is desirable to reduce voltages to be applied to the drain, the source and the control gate of the flash memory cell for the injection of the electric charges into the charge storage layer of the memory cell (for the writing operation) as much as possible. If a low-voltage operation is possible, there is no need to increase the gate width and length of a transistor in a decoder circuit involved in the operation of the memory cell to ensure a proper breakdown voltage and a proper driving current. Further, the reduction of the voltages to be applied for the writing operation makes it possible to reduce the size of a booster circuit provided in the chip. Thus, the size reduction of the decoder transistor and the booster circuit can be achieved, so that the area of the chip can be reduced.
One exemplary method for reducing the gate width and length of the decoder transistor is to reduce the magnitude of the voltage to be applied to the control gate while ensuring a proper potential difference between the control gate and the channel by applying a negative voltage to the drain. In the flash memory cell having the prior art structure, however, the application of the negative voltage to the drain forwardly biases a junction of the P-type semiconductor substrate (ground), resulting in an overcurrent. Therefore, the simple application of the negative voltage is impractical. A known approach to this is to provide the memory cell in a triple well structure, i.e., to form an N-well layer in the P-type semiconductor substrate and provide the memory cell in the N-well layer, for electrical isolation from the semiconductor substrate. However, this approach is disadvantageous in that the production process is complicated.
As described above, it is desirable that the voltages to be applied to the drain diffusion layer, the source diffusion layer and the control gates of the memory cells are reduced as much as possible in the nonvolatile memory device provided in association with the island semiconductor layer for the size reduction and the capacitance increase of the memory cells. Therefore, it is preferred to reduce the magnitude of the voltage to be applied to the control gates while ensuring a proper potential difference between the control gates and the channels by applying a negative voltage to the drain diffusion layer. In the prior art device structure shown in FIG. 7, however, the application of the negative voltage to the drain diffusion layer 7 forwardly biases a junction of the P-type semiconductor layer 12 (ground). Therefore, the simple application of the negative voltage is impractical. The provision of the triple well structure for the memory cells is a conceivable approach. In practice, however, the provision of the triple well structure in a lower portion of the P-type semiconductor layer 12 requires a more complicated production process than the prior art flash memory.